FAQ
From Milkymist Wiki
[edit] Do I need to know about FPGAs to participate in development?
Not at all. Once the FPGA is programmed, it contains a microprocessor which behaves like any other one. If you don't touch the FPGA at all, you can think of it as a powerful microcontroller containing graphics accelerators, which you can program using C or C++. See here for more details about what is inside the FPGA.
[edit] Do I always need to install FPGA tools?
No. If you only intend to do software development, you can download a pre-built binary bitstream and load it into your FPGA. The FPGA will then behave like any other system-on-chip or microcontroller.
[edit] What hardware do I need if I only want to do software?
A Milkymist One, a Xilinx JTAG cable (optional if your board is pre-flashed) and a 3.3V serial (RS232) cable.
[edit] How do I download my software into the system-on-chip?
The first program to be executed is the BIOS (bootloader), stored in NOR Flash. You can just flash one of the supplied images ; usually you don't have to modify this part. From there, you have many options. The most flexible one is the download over the serial port using the supplied flterm program. You can also write your binary image to a memory card and the system will boot from it. The boot process is detailed in the BIOS reference manual.
[edit] What compilers are supported?
GCC 4.5+ (experimental) or a patched earlier version (recommended). If you want to go the easy way, there is a binary toolchain for Linux/x86 in the SoC section.
[edit] What FPGA tools are supported?
ISE Webpack from Xilinx (free of charge) is sufficient. However, if you like big licenses, Milkymist ships with scripts to use with Synplify (Synopsys) and Precision (Mentor Graphics). They are not thoroughly tested, as I have very limited access to those tools.
[edit] Will using Synplify or Precision improve synthesis performance a lot?
Not really.
- Synplicity has a smaller runtime than Xst, but most of the time is spent in the place and route phase, which is always done using Xilinx's PAR tool. Precision has approximately the same runtime as Xst.
- Regarding area and timing, improvements are not dramatic. It seems that they tools beat Xst on code that makes heavy use of high-level constructs (such as GRLIB); but Milkymist is written in low-level hand-optimized HDL, on which big synthesizers perform only slightly better than Xst.
Support for those synthesizers is there only to evaluate them and to help tracking down particularly annoying bugs involving simulation/synthesis mismatches.
[edit] Can I use Altera/Lattice/Actel/XXX FPGAs?
With a little effort, yes. HDL code in this project is designed to be portable. Most design elements are inferred; and you will only need to replace elements that cannot be inferred such as PLLs.
Actel FPGAs might be slow, though.
[edit] What operating system is the system-on-chip running?
There are RTEMS and Linux available. The first devices will ship with RTEMS.
[edit] Do you intend to sell ready-for-use boards?
Yes, but no release date is currently defined.
[edit] What is the license for the code?
Most of it is covered by the GNU GPL v3.
[edit] FPGA projects are not really open source, you need a proprietary toolchain!
As far as Milkymist is concerned, the source code is standard Verilog HDL (compliant with the IEEE specification 1364-2005), is designed with portability as one of the first goals, has been shown to work almost unmodified on both major FPGA vendors (Altera and Xilinx), and can be simulated with many free and open source simulators (Icarus Verilog, GPL Cver, Verilator, VCOMP). Parts of the source code have even been shown to synthesize unmodified in TSMC 90nm cells with the Synopsys ASIC tools. Milkymist isn't more "Faux-pen Source" than all other open source software is because it requires a proprietary microprocessor to run.
The only problem with the FPGAs today is that no open source developer has ever stopped slacking to write a good toolchain. Everybody seems to prefer to keep whining about the FPGA bitstream format being closed, even though it isn't super-hard to reverse engineer (as far as Xilinx devices are concerned) and you do not even need to do that for the front-end synthesizer (which is incidentally the hardest part to write IMO) as all the primitives for the netlists are documented and the P&R and bitstream tools accept netlists in a standard format (IEC 61690-2).
[edit] How to contact the author?
Your suggestions, bug reports, bugfixes and patches are much appreciated. Information about how to contact the author is available on the page http://lekernel.net.
